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The digital logic families have come from the old simple resistor diode logic to the modern CMOS. In the recent time, many new Dynamic logic families have come up. These inventions are the result of the need to invent high speed logics. The static families though low on power dissipation, but are not too speedy. Therefore there is a need of dynamic logic families. In the dynamic Logic families on the other hand, it needs a clock signal for all the combinational circuits. This poses a serious problem in clock distribution but makes the circuits more synchronous. All the logic families vary in their certain parameters, like the speed, power, noise margin, circuit area, and above all the figure of merit. There is no family that can be used in all the design problems, some family may require less circuit area, but be too slow for a high speed design, on the other hand, one family may be high speed, but too costly on the circuit area parameter. In this work, transient and DC analysis of various families has been done.

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Mr. Ankush Chunn received his B.Tech degree from University of Jammu in 2006 and M.Tech degree from NIT Hamirpur in 2009. Currently, he is pursuing PhD in Department of ECE, NIT Jalandhar. His current areas of research are Mixed signal VLSI Design. He has published several conference and journal papers in this domain.

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