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Shojiro Asai

VLSI Design and Test for Systems Dependability


Herausgegeben von Asai, Shojiro
1st ed. 2019. 2018. xvii, 800 S. 233 SW-Abb., 352 Farbabb., 20 Farbtabellen. 235 mm
Verlag/Jahr: SPRINGER, BERLIN; SPRINGER JAPAN; SPRINGER 2018
ISBN: 4-431-56592-2 (4431565922)
Neue ISBN: 978-4-431-56592-5 (9784431565925)

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This book discusses the new roles that the VLSI (very-large-scale integration of semiconductor circuits) is taking for the safe, secure, and dependable design and operation of electronic systems.

The book consists of three parts. Part I, as a general introduction to this vital topic, describes how electronic systems are designed and tested with particular emphasis on dependability engineering, where the simultaneous assessment of the detrimental outcome of failures and cost of their containment is made. This section also describes the related research project "Dependable VLSI Systems," in which the editor and authors of the book were involved for 8 years. Part II addresses various threats to the dependability of VLSIs as key systems components, including time-dependent degradations, variations in device characteristics, ionizing radiation, electromagnetic interference, design errors, and tampering, with discussion of technologies to counter those threats. Part III elaborates on the design and test technologies for dependability in such applications as control of robots and vehicles, data processing, and storage in a cloud environment and heterogeneous wireless telecommunications.

This book is intended to be used as a reference for engineers who work on the design and testing of VLSI systems with particular attention to dependability. It can be used as a textbook in graduate courses as well. Readers interested in dependable systems from social and industrial-economic perspectives will also benefit from the discussions in this book.
Part I Threats against and Mitigation for Dependability.- Scope of Part I.- Radiation-Induced Soft Errors.- Electromagnetic Noises.- Variations in Device Characteristics.- Time-Dependent Degradation in Device Characteristics.- Connectivity.- Responsiveness.- Security.- Test Coverage.- Future and/or Un-Identified Problems. Part II Scope of Part II.- Design Verification.- Virtualization.- In-Line Testing.- Robust Memory 1 - SRAM and Cache.- Robust Memory 2 - Non-Volatile.- 3D Integration.- On-Chip Network for Dependability.- Wireless Interconnect for Connectivity.- Hard Real-Time Responsive Processor.- Connectivity in Wireless Communications.- A Re-Configurable Processor Architecture.- Security Component for Authentication.