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PART I: Design
# 01 3D Design Styles
# 02 Ultra-Fine Pitch 3D-Stacked Integrated Circuits: Technology, Design Enablement and Application
# 03 Power Delivery Network and Integrity in 3D IC Chips
# 04 Multiphysics Challenges and Solutions for Design of Heterogeneous 3D-Integrated Systems
# 05 Physical Design Flow for 3D/CoWoS¨ Stacked ICs
# 06 Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D Ics
# 07 Electronic Design Automation for 3D # 08 3D Stacked DRAM Memories

PART II: Test
# 09 Cost Modelling for 2.5D and 3D Stacked ICs
# 10 Interconnect Testing for 2.5D- and 3D-SICs
# 11 Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps
# 12 3D Design-for-Test Architecture
# 13 Optimization of Test-Access Architectures and Test Scheduling for 3D ICs
# 14 IEEE P1838 3D Test Access Standard-in-Development
# 15 Test and Debug Strategy for TSMC CoWoS¨ Stacking Process Based Heterogeneous 3D IC: A Silicon Study
PART III: Thermal Management
# 16 Thermal isolation and cooling technologies for heterogeneous 3-D and 2.5-D ICs
# 17 Passive and Active Thermal Technologies: Modeling and Evaluation
# 18 Thermal Modeling and Experimental Model Validation for 3D Stacked ICs
# 19 On the Thermal Management of 3D ICs: from back-side, to volumetric heat removal

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This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective.
Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.

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PART I: DESIGN
3D Design Styles
Design Enablement and Advantages of Ultra-Fine Pitched 3D-Stacked Integrated Circuits
Wyoming Case Study
IBM Interposers
Interposer Interconnect Circuits
Signal Integrity for 3D
Power Integrity for 3D
2.5D/3D Design Flow
Monolithic 3D
EDA for 3D
3D Memories
3D Clock Distribution
PART II: TEST
Cost Modelling for 2.5D and 3D Stacked ICs
Interconnect Testing for 2.5D and 3D Stacked ICs
Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps
3D Design-for-Test Architecture
Optimization of Test-Access Architectures and Test Scheduling for 3D ICs
IEEE P1838 3D Test Access Standard-in-Development
Test and Debug Strategy for TSMC CoWoS Stacking Process Based Heterogeneous 3D IC: A Silicon Case Study
PART III: THERMAL MANAGEMENT
Thermal Challenges and Emerging Solutions for 3D and 2.5D IC
Thermal Modeling and Experimental Model Validation for 3D Stacked ICs
Thermal Design for 3D ICs with Micro-Fluidics

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