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Metal gates are expected to replace polysilicon gates beyond the 45nm technology node in order to achieve equivalent oxide thickness 1nm. Poly silicon gates suffer depletion effect, high resistivity, and boron penetration. Moreover, polysilicon gates are not compatible with high-k dielectric. Metal/high-k stack can save these issues and become the solution of gate stack for the sub 45nm technology node. The requirements of metal gates include several main factors, such as suitable work function, compatibility with high-k dielectric, thermal stability and simple process integration. For suitable threshold voltage, metal gates with tunable work function are preferred, of which work function should be in the range of 4.1-4.4eV for NMOSFETs and 4.8-5.1eV for PMOSFETs. High thermal stability is expected to avoid chemical reaction with gate dielectric and the surrounding insulators. Metal gates have been realized by two approaches: gate-first and gate-last. The former approach is superior due to its simple fabrication. The latter, also called replacement gate, uses a dummy gate etched and replaced by the metal gate after the front-end process.

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Chih Feng Huang was born in 1975 in Taiwan. He recieved his B.S. degree in control engineering, M.S. degree and Ph.D. degree in electronics engineering from National Chiao Tung University Taiwan in 1997, 2001 and 2006, respectively.

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