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System Level Simulation of an IP is necessary to ensure it´s reliability and robustness. Since the speed of the integrated devices is increasing in an exponential manner, Signal Integrity (SI) effects and Power Integrity (PI) effects, resulting in (BER) take place at a considerable level. In high speed digital devices, Signal Integrity (SI) and Power Integrity (PI) are the most important factors for the designers to keep in the mind while designing a system, as they affect the reliability of transmission at high data rates. This research work intends to analyze SI and PI for On-the-Board System emphasizing on reliability and robustness analysis of PHY IP for high speed data operations. The speed of the systems is increasing but the voltage supplied is being reduced. There are more and more complex routing structure being used. This complication at higher speeds results in reflection, crosstalk, EMI and other high frequency effects. The uninterrupted power supply in such complex structures is called PI. This book takes into the account both SI and PI at system level.

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Jai Narayan Tripathi was born in Gangapur (Bhilwara), a town in Rajasthan, India. He received his B.E. in 2007 and M.Tech from DA-IICT, Gandhinagar in 2009. At present he is a Ph.D Scholar at IIT Bombay, Mumbai. His areas of interest are Signal Integrity and RF Circuits Optimization. Apart from academics, his hobbies are Creative Writing and Music.

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