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Revision with unchanged content. This theses addresses the various tradeoffs involved when designing SRAM s. Each component of the SRAM is looked at in detail and various tradeoffs explored. The key to low power operation in the SRAM data path is to reduce the signal swing on the high capacitance nodes like the bitlines and the data lines. A unique resetting scheme for the row decoders has been proposed. Using this technique the word line pulse width can be minimized and the signal swings on the bitlines reduced. Finally a 4Kb prototype SRAM has been designed and verified. This design incorporates some of the circuit techniques used to reduce power dissipation and delay. Experimental data has been provided which shows the effectiveness of using the resetting scheme for the row decoders. The book is addressed to professionals and students in the semi-conductor industry and especially those in circuit design. It is also directed towards researchers in memory cell design and memory architecture design.

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Design Engineer, Master of Science in Computer Engineering from North Carolina State University. Currently working at Broadcom Corporation, Irvine.

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