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This book summarizes the outcome of investigations on the effects of aging mechanisms induced parameter shifts and performance degradation in analog and mixed signal integrated circuits. Degradation induced due to aging mechanisms like bias temperature instability, conducting and non-conducting hot carrier injection in NMOS and PMOS devices leads to increased challenges in design of reliable circuits in deep-submicrometer CMOS technologies. The lifetime degradation induces threshold voltage and drain current shifts that can result into mismatch in matched transistor pairs which is especially important for analog and mixed signal circuit´s accuracy. The investigations are done based on analytical evaluation, aging simulation and measurements using sample circuits implemented in state-of-the-art 32nm high-k metal gate CMOS technology. Calibration and correction techniques suitable for overcoming time varying aging induced circuit performance degradation are proposed and investigated. This book is structured to guide the reader from important aging mechanisms, over to aging degradation in analog and mixed signal building blocks and countermeasures to overcome these effects.

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Shailesh More obtained the Dr.-Ing. degree in 2012, while working as a research engineer at Institute of Technical Electronics of Technische Universität München. He obtained MSc. degree in IC design under a joint program between TUM, Germany and NTU, Singapore in 2009. He has worked in Wirpo, TI and Infineon Technologies in the field of IC design.

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