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Scalable packet-switched Network-on-Chip (NoCs) are essential in undertaking the role of the communication medium in modern many-core systems. Consequently, the reliability of the NoC is critical for the operation of the system. In this work, we develop, design, implement, and investigate the NoCAlert engine at the Register Transfer Level (RTL). NoCAlert is a mechanism that can detect illegal decisions in the various components of the NoC router micro-architecture, based on the components normal operation specifications. The fault-detection hardware engine is developed in synthesizable Hardware Description Language (HDL) form and it is based on modular checkers. We propose the deployment of various such cooperating checkers within the major components of the networks routers to observe the NoCs behaviour at run-time. The operation and detection capabilities of this mechanism are based on an on-line and real-time monitoring methodology, which provides full error coverage with almost instant detection of the faults upon manifestation. By targeting major components in each router we are able to provide a hardware-based protection blanket that can lead to a robust network.

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Andreas Panteli holds a BSc and an MSc in Computer Engineering from the University of Cyprus. During his post graduate studies he was focused on the design of the reliability framework for Networks on Chip (NoCs). Currently, he is an HPC Systems Support Specialist at The Cyprus Institute, Nicosia, Cyprus.

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