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This book aims at digital logic optimization and synthesis issues from the aspects of low power, area and testability. The issue of logic optimization which is essentially a technology-independent optimization has been addressed in different chapters are based on the research problems, which include, two-level logics, multi-level logics, AND-OR/XOR based logics, BDDs,and Finite State Machines synthesis. Genetic Algorithms have been extensively used to frame the problems and to derive the best solution of it. The topics presented in each of the chapters from 3-7 are based on the research carried out in each of the areas mentioned earlier. I am sure that the book will be quite useful to readers interested in logic minimization and to researchers who are interested in doing research in the area of low power VLSI and like to carry out further work in the field of logic optimization and synthesis.

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Graduated in Electrical Enginnering from REC, Silchar, India under Gauhati University in 1993-94. Subsequently, obtained his Masters and Ph.D degree in the field of Microelectronics and VLSI Design from IIT Kharagpur in 2001 and 2009. He is a member and reviewer of IEEE and published more than 30 research papers in Int. Journals and Conferences.

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