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This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage.

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Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.

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Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes.- Existing Leakage Minimization Approaches.- Computing Leakage Current Distributions.- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities.- The HL Approach: A Low-Leakage ASIC Design Methodology.- Simultaneous Input Vector Control and Circuit Modification.- Optimum Reverse Body Biasing for Leakage Minimization.- I: Conclusions and Future Directions.- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design.- Exploiting Leakage: Sub-threshold Circuit Design.- Adaptive Body Biasing to Compensate for PVT Variations.- Optimum VDD for Minimum Energy.- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining.- II: Conclusions and Future Directions.- Design of a Sub-threshold BFSK Transmitter IC.- Design of the Chip.- Implementation of the Chip.- Experimental Results.

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