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Based on a new family of logic, this volume presents a completely new approach to implementing ultra-low-power integrated circuits. The text carefully describes how new techniques can be used for digital and analog ultra-low-power design, and includes experimental results.

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Design exibility and power consumption in addition to the cost, have always been the most important issues in design of integrated circuits (ICs), and are the main concerns of this research, as well. Energy Consumptions: Power dissipation (P ) and energy consumption are - diss pecially importantwhen there is a limited amountof power budgetor limited source of energy. Very common examples are portable systems where the battery life time depends on system power consumption. Many different techniques have been - veloped to reduce or manage the circuit power consumption in this type of systems. Ultra-low power (ULP) applications are another examples where power dissipation is the primary design issue. In such applications, the power budget is so restricted that very special circuit and system level design techniquesare needed to satisfy the requirements. Circuits employed in applications such as wireless sensor networks (WSN), wearable battery powered systems [1], and implantable circuits for biol- ical applications need to consume very low amount of power such that the entire system can survive for a very long time without the need for changingor recharging battery[2-4]. Using newpowersupplytechniquessuchas energyharvesting[5]and printable batteries [6], is another reason for reducing power dissipation. Devel- ing special design techniques for implementing low power circuits [7-9], as well as dynamic power management (DPM) schemes [10] are the two main approaches to control the system power consumption. Design Flexibility: Design exibility is the other important issue in modern in- grated systems.

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Scalable and Ultra-Low-Power Digital Integrated Circuits.- Subthreshold Source-Coupled Logic.- STSCL Standard Cell Library Development.- Subthreshold Source-Coupled Logic Performance Analysis.- Low-Activity-Rate and Memory Circuits in STSCL.- Subthreshold MOS for Ultra-Low Power.- Scalable and Ultra-Low-Power Analog Integrated Circuits.- Widely Adjustable Continuous-Time Filter Design.- Scalable Folding and Interpolating ADC Design.- Widely Adjustable Ring Oscillator Based ?? ADC.- Wide Tuning Range PLL.- Conclusions.

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