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Dynamic logic circuits have been popularly used in advanced high speed processors as they occupy less area and have higher speed in comparison with the static CMOS counterparts. Domino logic is one of the popular dynamic logic. The major problems with domino gates are higher dynamic power, static power and lower noise immunity than static logic circuits. In this work, an attempt has been made to design novel circuit techniques for robust, energy-efficient and high performance domino logic circuits in deep submicron technology. All the existing and proposed techniques have been simulated and tested using VLSI back end tools. The logic swing at the output, power dissipation, propagation delay, PDP, area, and noise margins have been evaluated. The study has been carried in 65 nm technology at clock frequencies of 0.05 to 1.5 GHz. The attempt of designing novel circuit techniques for robust, energy-efficient, and high performance domino logic circuits in DSM technology has been achieved. The designed circuits are having better results than the existing circuits in terms of power dissipation, propagation delay, PDP, and noise immunity.

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Salendra Govindarajulu is working as a Professor in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal, Andhra Pradesh, India. He completed B.Tech (ECE) from RGMCET, NANDYAL, JNTUH, A.P., INDIA in 1999. He completed M.Tech from NITC, Calicut, KERALA, INDIA in 2001. He completed Ph.D in Low Power VLSI Design from JNTUH, Hyderabad.

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