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Adders are the basic building blocks of any processor or data path application. In adder design, carry generation is the critical path. To reduce the power consumption of the data path, we need to reduce the area of the adder. Carry Select Adder is one of the fast adders used in may data path applications. The proposed design is implemented without using multiplexer and RCA structure with Cin=1. Instead of using multiplexer and RCA Cin=1 structure, we use simple combinational circuit. After speed, power dissipation is one of the most important design objectives in integrated circuits. As adders are the most widely used components in such circuits, the design of efficient adder is of much concern for researchers.
This paper presents a performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters, i.e. Area, Speed and Power consumption. We also show a modified carry select adder designed at different stages.

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Chapter 3 DESIGN OF MULTI- BIT FULL ADDER USING DIFFERENT LOGIC:
3.1: 4-BIT FULL ADDER:
The 4-bit adder block used in CSA is ripple carry adder. In ripple carry adder each carry bit from a full adder "ripples" to the next full adder [3]. The simple implementation of 4-bit ripple carry adder is shown below in Figure 2. C0 is the input carry, x3 x2 x1 x0 and y3 y2 y1 y0 represents two 4-bit input binary numbers.C4 is the output carry and s3 s2 s1 s0 is the sum output.
The ripple carry adder is designed using a full adder cell with 18-transisitors based on transmission gate logic [4]. The full adder is constructed using an XOR gate and two 2:1 multiplexers as shown in Figure 3.1.1.The SUM (A xor B xor Cin) is formed by a multiplexer controlled by A xor B (and complement). Examining the adder truth table reveals that when A xor B is true, COUT=C and SUM=complement of C. When A xor B is false, COUT=A (or B) and SUM=C. The ripple carry adder is designed using a full adder cell with 18-transisitors based on transmission gate logic [4]. The full adder is constructed using an XOR gate and two 2:1 multiplexers as shown in Figure 3.1.2.The SUM (A xor B xor Cin) is formed by a multiplexer controlled by A xor B (and complement). Examining the adder truth table reveals that when A xor B is true, COUT=C and SUM=complement of C. When A xor B is false, COUT=A (or B) and SUM=C.
It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder (under the assumption that Cin = 0).
The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 x 2 (for carry propagation in later adders) = 65 gate delays. The delay from bit position 0 to the carry-out is a little different: The carry-in must travel through n carry-generator blocks to have an effect on the carry-out A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as fast. [...].

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Pinaki Satpathy has received his Bachelors Degree B.Tech in Electronics and Communication Engineering from Biju Patnaik University of Technology, Orissa, in 2005. He achieved his Master´s Degree M.Tech in Embedded System at West Bengal University of Technology, Kolkata, in 2010. His research interest is in the fields of Digital VLSI Design, Low Power VLSI Design, Network-on-chip (NOC) Design, etc. Presently, the author is serving as Assistant Professor in the Department of Electronics and communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India. He has more than eight international publications and two books published so far.

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